Safety Levels-An Efficient Mechanism for Achieving Reliable Broadcasting in Hypercubes

[4] Alphu urchitecture hundbook, Digital Equipment Corporation, Maynard, MA, 1992. [SI T.-Y. Yeh and Y.N. Patt, “Two-level adaptive training branch prediction,” Proc. 24th ACMIIEEE Int ’1 Symp. and Workshop on Microarchitecture, pp. 51-61, Nov. 1991. [6] T.-Y. Yeh and Y.N. Patt, “Altemative implementations of two-level adaptive branch prediction,” Proc. 19th Annual Int’l Symp. on Computer Architecture, pp. 124-134, May 1992. [7] S.-T. Pan, K. So, and J.T. Rahmeh, “Improving the accuracy of dynamic branch prediction using branch correlation, ” Proc. 5th Int’l Conference on Architectural Support for Programming Languages und Operating Systems, pp. 76-84, Oct. 1992. [8] T.-Y. Yeh and Y.N. Patt, “A comparison of dynamic branch predictors that use two levels of branch history,” Proc. 20fh Annual Int’l Symp. on Computer Architecture, pp. 257-266, May 1993. [9] R. Nair, “Branch behavior on the IBM RISC Systed6000,” Reseurch Report RC 17859, IBM T.J. Watson Research Center, Yorktown Hts., NY, Apr. 1992. [IO] C.G. Ponder, “Studies in branch prediction,” Report UCRL-ID-106077, Lawrence Livermore National Laboratory, Sept. 1990. [ I I] G.F. Grohoski, “Machine organization of the IBM RISC Systed6000 processor,” IBM Joumul of Research and Development, vol. 34, no. I , pp. 37-58, Jan. 1990. S. McFarling and J. Hennessy, “Reducing the cost of branches,” Proc. 13th Annual Int’l Symp. on Computer Architecture, pp. 396-403, June 1986. [ 131 D.J. Lilja, “Reducing the branch penalty in pipelined processors,” IEEE Computer, pp. 47-55, July 1988. [I21